This application claims the priority of Korean Patent Application No. 2003-55363, filed on Aug. 11, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a high voltage transistor used in a peripheral circuit of a flash memory device or an Electrically Erasable and Programmable Read Only Memory (EEPROM) device that is a nonvolatile memory device operating at a high voltage, and a method of manufacturing the same.
2. Description of the Related Art
When a semiconductor integrated circuit directly controls an external system using a high voltage, the integrated circuit requires a high voltage control device to which the external system directly applies the high voltage, and a circuit needing a high breakdown voltage requires a specific high voltage device. For example, since a cell of an EEPROM uses F-N (Fowler-Nordheim) tunneling for operation, a high voltage is required when a program operation or an erase operation is performed. It is essential that a device needing high voltage for operation use a high voltage transistor in a peripheral circuit.
Various technologies required for performing an operation of a nonvolatile memory cell have been proposed for improving the performance of high voltage transistors used in the peripheral circuit. Examples of such technologies are found in U.S. Pat. Nos.: 5,917,218 and 6,071,775).
To allow a drive transistor used to drive the external system having the high voltage directly applied thereto to smoothly drive the external system, a breakdown voltage between a drain of the high voltage transistor and the semiconductor substrate should be greater than a high voltage applied to the drain. An important parameter for determining the breakdown voltage of the drain to which the high voltage is applied is a separation distance between a gate electrode and a high concentration junction.
In one example of the conventional art, a mask islanded double diffused drain (MIDDD) structure is employed in the drain region to elevate the breakdown voltage, thereby implementing a high breakdown voltage junction structure.
FIG. 1 is a sectional view illustrating a principal part of a conventional high voltage transistor 10 employing a MIDDD structure. In FIG. 1, a structure of the high voltage transistor 10 constituting an NMOS transistor is exemplified.
Referring to FIG. 1, a drain region 16 formed in a P-type silicon substrate 12 has a double structure having a low concentration drain region 16a and a high concentration drain region 16b. In this structure, high concentration implantation is performed using a photoresist pattern so as to secure enough separation distance (X1) between the gate electrode 20 and the high concentration drain region 16b. 
If the photoresist pattern is used at the time of the high concentration implantation so as to secure the separation distance (X1) between the gate electrode 20 and the high concentration drain region 16b as in the conventional art, a misalign margin (X2) should be considered for the separation distance (X1) and an overlap between the high concentration drain region 16b and a contact 30 in a photolithographic process for forming the photoresist pattern. Accordingly, a layout is required to have a size corresponding to a design rule considering the misalign margin (X2). This causes the high voltage transistor to increase in size.
In a logic transistor, a salicide (self-aligned silicide) process is generally applied to a contact region for a high-speed operation. The salicide process has an advantage in that if it is also applied to the high voltage transistor of the peripheral circuit region, the performance of the high voltage transistor can be improved. However, as exemplified in the conventional art of FIG. 1, if the photoresist pattern is used at the peripheral circuit region to secure the separation distance (X1) between the gate electrode 20 and the high concentration drain region 16b, it is impossible to apply the salicide process for embodying a high speed logic transistor to the entire surface of a wafer. That is because if the salicide process is applied to the high voltage transistor 10 shown in FIG. 1, siliciding is performed up to on a surface of the low concentration drain region 16a such that the low concentration drain region 16a is caused to be directly biased thereby greatly reducing the breakdown voltage.